Thin film silicon solar cells can be produced in superstrate (pin) and substrate (nip) configurations, with structures consisting of stacked cells in pin-pin or nip-nip configurations with two or more than two stacked cells to produce multi-junctions solar cells. The thin film silicon cells are hydrogenated amorphous silicon (a-Si:H) and hydrogenated microcrystalline silicon (μc-Si:H) cells, which can thus be used in stacked conjunction in order to optimize the use of the full solar spectrum, allowing for improved efficiencies. The development of high-efficiency thin-film silicon solar cells in the different configurations then requires a cell design allowing for a high light trapping while maintaining optimum cell electrical properties. An improved light management in the cells is decisive in order to lead to increased effective light paths in the absorbing film and thus to the possible use of thinner photo-active layers in the cells. While this is important for production throughput and cost reduction, improved light trapping and the use of thin intrinsic layers are mandatory to achieve higher conversion efficiencies because of inherent material properties. For hydrogenated amorphous silicon (a-Si:H), the impact onto the cell performance of the light induced degradation of the bulk material (Staebler-Wronski effect) can be reduced in thinner films. In the case of microcrystalline silicon (μc-Si:H), light trapping is mandatory to compensate the low absorption due to the indirect band-gap, so as to allow for the use of μc-Si:H layers with thicknesses not impacting the cell electrical properties.
Light trapping is obtained by introducing a textured interface, either by having a glass substrate coated with transparent and nanotextured materials or by coating an opaque substrate with a rough structure. The light is scattered at the rough interfaces, in transmission and/or in reflection at the textured interfaces of the structure. This scattering can increase the effective path length of each photon through the absorber layer (if the light diffusion takes place at high angles) and can lead to multiple internal reflections in the devices. These two combined effects lead to light trapping in the solar cell and can multiply the optical thickness of the absorber layer without requiring an increase in the physical thickness of the photo-active layer. Typical values for the light path enhancement of 5 to 20 are reported in the literature. The typical lateral feature size (D) and root-mean-square (rms) roughness (Rrms) of the features required for light trapping in a-Si:H cells are in the range of D=100-300 nm and Rrms 50-200 nm, and for the μc-Si:H and multi-junction cells incorporating a μc-Si:H junction in the range of D=200-2000 nm and Rrms=50-500 nm.
Several textured surfaces of either the substrate or of the transparent conductive oxide (TCO) layer that precede the silicon deposition were developed demonstrating enhanced light management and therefore increased short circuit current densities in both a-Si:H and μc-Si:H based thin film silicon solar cells. Textured SnO2 deposited by APCVD, sputtered-etched ZnO, low pressure chemical vapor deposition (LPCVD) ZnO are such demonstrated solutions. For instance, LPCVD ZnO films are polycrystalline films constituted of large grains, with a surface characterized by large pyramidal features, which provide to LPCVD as-grown ZnO good light scattering ability. The pyramidal features characteristics of the layers can be varied by a control of the growth conditions and by variations of the layer thickness, resulting in a control over which wavelengths are preferentially scattered.
In all generality though, there is strong drawback of most light scattering schemes.
A strong problem that occurs in the realization of devices is that when rough structures are introduced to realize an efficient light scattering, they also tend to create in-homogeneities and defects in the absorber layers of the solar cell, resulting in possible local current drains such as low-quality diodes or physical shunts. This effect was shown to be universal and applies for all rough (rms>50 nm) superstrates and susbtrates electrodes presenting “sharp” features in the sense of valley with short radius of curvature (typically smaller than 100 nm) or facets with inclinations higher than 20°. This is particularly true for the μc-Si:H cell which is particularly affected by the substrate morphology.
In particular, μc-Si:H solar cells deposited on rough LPCVD ZnO, or rough SnO2, or rough pyramidal structures, suffer from losses in VOC and FF, caused by the local low-quality materials formation resulting from the rough substrate morphology. As almost always, for instance when increasing the roughness of the ZnO, the short circuit current (JSC) of cells increases, but the efficiency is not maximized due to the losses in VOC and FF. Conversely, μc-Si:H cells prepared on flat substrates show very high VOC and FF, but suffer from sub-optimal JSC. This is also true for solar cells prepared on opaque back-reflector.
This effect, which is detrimental for microcrystalline silicon cell, was demonstrated to have a strong impact in multi-junction solar cells. After the growth of the amorphous silicon top cells, cracks continue to propagate or even start to grow in the microcrystalline silicon layer. Hence, it is particularly true for multi-junctions devices that the growth of the a-Si:H cell, possibly of the intermediate reflector and of the recombination junction can lead to a surface morphology even more prone to induce cracks and low quality material regions in the growth of the subsequent microcrystalline silicon cell. This leads to strong reduction of VOC and FF. Indeed many solar cell production lines worldwide are fighting with this effect. Hence it is of critical importance to avoid the detrimental effects of such cracks in the multi-junctions cell.
A first approach to accommodate for the local low-quality materials regions acting as local current drains is therefore to reduce their density in the solar cell. This has to be done while not impacting too strongly the substrate morphology in order to conserve a good light trapping. This can be realized to some extent via optimizations of the deposition process in order to have a bulk material growth more adapted to sharp surface features. Another solution is to modify the textured surface morphology in order to smooth the sharp valleys while maintaining the peak textures. This can be realized for cells incorporating textured LPCVD ZnO by applying a post-plasma treatment that will smooth the surface. If the radius of curvature at the bottom of the valley is reduced, the VOC and FF are increased thanks to a reduction of the density of the local low-quality material regions. A drawback of such solution is however that the texture is modified; therefore lowering the light trapping potential and decreasing short circuit current density. Finally and in more general terms, the use of textured substrates with a reduced roughness also allows for a decreased density of local current drains, the amorphous silicon top cell can even tend to slightly smoothen out the initial surface if the surface texture dimensions are lower to that of the cell. However, a less pronounced texture will here again lead to a reduced light trapping potential. The optimum textured surface has therefore to lead to an optimum tradeoff between light trapping ability (short circuit current) and density of low-quality material regions and local current drains (VOC and FF). Such optimum texture is difficult to achieve and none of the actual developed solutions have permitted such breakthrough.
In conclusion, a controlled growth of a high material quality can first result in improved performance of μc-Si:H cells onto textured substrates. However, while it does not show to be sufficient for highly textured substrates which have higher light trapping potential, this optimization of the deposition process require precise deposition conditions, therefore rendering the cell properties and reliability sensitive to drift in deposition process and to non-uniformities in the reactor, strongly impacting yield and robustness of the cell design. Finally, the reduction of the density of locally low quality diodes can be realized with proper optimization of the structured interface, but always at the price of reduced light trapping potential.